jmke

This article provides a technical look at the challenges in scaling chip production ever downward in the semiconductor industry. Chips based on a 22nm process are running in consumer devices around the world, and 14nm development is well underway. But as we approach 10nm, 7nm, and 5nm, the low-hanging fruit disappears, and several fundamental components need huge technological advancement to be built. Quoting: "In the near term, the leading-edge chip roadmap looks clear. Chips based on today's finFETs and planar FDSOI technologies will scale to 10nm. Then, the gate starts losing control over the channel at 7nm, prompting the need for a new transistor architecture. ... The industry faces some manufacturing challenges beyond 10nm. The biggest hurdle is lithography. To reduce patterning costs, Imec's CMOS partners hope to insert extreme ultraviolet (EUV) lithography by 7nm. But EUV has missed several market windows and remains delayed, due to issues with the power source. ... By 7nm, the industry may require both EUV and multiple patterning. 'At 7nm, we need layers down to a pitch of about 21nm,' said Adam Brand, senior director of the Transistor Technology Group at Applied Materials. 'That's already below the pitch of EUV by itself. To do a layer like the fin at 21nm, it's going to take EUV plus double patterning to round out of the gate. So clearly, the future of the industry is a combination of these technologies.'

http://hardware.slashdot.org/story/1...-really-happen

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