SK Hynix Licenses DBI Ultra Interconnect for Next-Gen 3DS and HBM DRAM

Stefan Mileschin · 12th February 2020, 12:49

SK Hynix has inked a new broad patent and technology licensing agreement with Xperi Corp. Among other things, the company licensed the DBI Ultra 2.5D/3D interconnect technology developed by Invensas. The latter was designed to enable building up to 16-Hi chip assemblies, including next-generation memory, and highly-integrated SoCs that feature numerous homogeneous layers.

Invensas’ DBI Ultra is a proprietary die-to-wafer hybrid bonding interconnect technology that supports from 100,000 to 1,000,000 interconnects per mm2, using interconnect pitches as small as 1 µm. According to the company, the much greater number of interconnects can offer dramatically increased bandwidth vs. conventional copper pillar interconnect technology, which only goes as high as 625 interconnects per mm2. The small interconnects also offer a shorter z-height, making it possible to build a stacked chip with 16 layers in the same space as conventional 8-Hi chips, allowing for greater memory densities.

https://www.anandtech.com/show/15498...n-3ds-hbm-dram

12th February 2020, 12:49	#1
Stefan Mileschin [M] Reviewer Join Date: May 2010 Location: Romania Posts: 153,541	SK Hynix Licenses DBI Ultra Interconnect for Next-Gen 3DS and HBM DRAM SK Hynix has inked a new broad patent and technology licensing agreement with Xperi Corp. Among other things, the company licensed the DBI Ultra 2.5D/3D interconnect technology developed by Invensas. The latter was designed to enable building up to 16-Hi chip assemblies, including next-generation memory, and highly-integrated SoCs that feature numerous homogeneous layers. Invensas’ DBI Ultra is a proprietary die-to-wafer hybrid bonding interconnect technology that supports from 100,000 to 1,000,000 interconnects per mm2, using interconnect pitches as small as 1 µm. According to the company, the much greater number of interconnects can offer dramatically increased bandwidth vs. conventional copper pillar interconnect technology, which only goes as high as 625 interconnects per mm2. The small interconnects also offer a shorter z-height, making it possible to build a stacked chip with 16 layers in the same space as conventional 8-Hi chips, allowing for greater memory densities. https://www.anandtech.com/show/15498...n-3ds-hbm-dram

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