Stefan Mileschin

Samsung on Tuesday introduced its sixth-generation V-NAND memory with over 100 active layers. To make V-NAND with over 100 layers viable from performance point of view, the company had to use new circuit design technology. The new memory features 10% lower latencies and consumes 15% lower amount of power when compared to previous-generation V-NAND.

Samsung’s 6th Generation V-NAND features up to 136 layers as well as charge trap flash (CTF) cells. The new memory uses one stack and does not use technologies like string stacking to build over 100 layers. In order to ensure lack of errors and low latencies, Samsung had to use a new speed-optimized circuit design. The latter enabled the new 3D TLC 256 Gb chips to offer below 450 microseconds (μs) latency for write operations and below 45 μs for read operations, which is 10% faster when compared to 5th Generation V-NAND, according to Samsung. Meanwhile, the latest V-NAND also features lower power consumption than its predecessors.

It is noteworthy that the new 256 Gb 136-layer V-NAND devices use 670 million holes, down from 930 million holes with the previous generation, which means that the new chips need less process steps and are easier to manufacture. What is important is that Samsung plans to use its 136-layer architecture with speed-optimized circuit design to build V-NAND devices with over 300 layers by mounting three of the current stacks on top of each other (thus tripling a chip’s capacity).

Initially, Samsung will offer 256 Gb 3D TLC 136-layer V-NAND devices that will first be used for Samsung’s 250 GB SSDs. Later this year Samsung intends to release 512 Gb 136-layer V-NAND devices that will be used for other drives as well as eUFS storage solutions.

Speaking of the 256 GB 6th Gen V-NAND SSD, it is important to point out that it uses Samsung’s new controller marked as the S4LR030/S94G4MW2.

https://www.anandtech.com/show/14721...-to-136-layers