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Intel may have plans to introduce Xeon processors for 2-way applications with 1066MHz bus next year and already discusses chipsets with support for such PSB with certain partners, The Register web-site reports.

Later this year Intel is expected to unveil Xeon processors with 1MB L2 cache, Enhanced Memory 64 Technology, 800MHz Quad Pumped Bus as well as appropriate chipsets code-named Lindenhurst (E7320, E7520) and Tumwater (E7525) to support the launch. Next year Intel is likely to commercially unveil Xeon processors with 1066MHz processor system bus with appropriate chipsets code-named Blackford and Greencreek, The Register quotes a presentation from Intel’s Tommy Rydendahl. The timeframe for the new core-logic sets introduction is described as mid-2005 or beyond.

Intel recently canned the successors of Pentium 4 and Xeon processors code-named Tejas and Jayhawk in favour of dual-core chips. Nevertheless, the company added Pentium 4 “Prescott 2M” and Xeon “Irwindale” processors into the lineup, according to various reports. The Prescott 2M is projected to have 2MB L2 cache and utilize 1066MHz PSB in addition to some other enhancements, the Irwindale is also anticipated to feature 2MB L2, but to feature 800MHz Quad Pumped Bus.

The new flavour of Pentium 4 with 2MB cache will be available in Q4 2004, according to the previous reports at X-bit labs. The Irwindale chips are slated for Q1 2005 introduction.

It is not clear whether Intel plans to enter dual-core processors with 1066MHz processor system bus or revamp some higher-end Xeon “Irwindale” chips to support faster QPB bin.

Intel’s officials did not comment for the report.

http://www.xbitlabs.com/news/cpu/dis...525093525.html

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