Stefan Mileschin

Developed a soft IP microcontroller core

Intel has developed a soft IP microcontroller core for its FPGAs using the RISV-V instruction set

The Nios V processor is the next generation of a soft processor for Intel’s Cycline, Stratix and Aria FPGAs based on the open-source RISC-V Instruction Set Architecture. This processor is available in the Intel Quartus Prime Pro Edition Software, starting with version 21.3. This follows the 32bit Nios II, launched over a decade ago by Altera in Quartus 8.

For those who came in late, the Nios V is based on RISC-V: RV32IA architecture designed for performance, with atomic extensions, a 5-stage pipeline, and AXI4 interfaces.

The first version is the Nios V/m microcontroller. This has a benchmark performance of 0.46 DMIPS/MHz and 16 CoreMarks, making it about half the performance of an ARM M0+ core but comparable to other RV32 implementations. However, the benchmarking is less relevant as instruction extensions can be added in the FPGA fabric to boost performance for specific applications.

Intel is working on a general-purpose application class processor called the Nios V/g to run operating systems like Linux, presumably with a memory management unit.

https://fudzilla.com/news/53661-inte...into-high-risc