jmke

Intel said that it was able to fine tune its DRAM design and hit a physical clock of 2 GHz using a 65 nm manufacturing process. The resulting 2T-DRAM offers a stunning bandwidth of 128 GB/s. If Intel is successful to take the clock speed up to the level of its QX9770/9775 processors, the bandwidth would climb to 204.8 GB/s. In other words: Intel would gain more than a 10x improvement over its current L2 cache technology. More importantly: This approach would completely change the programming model since there are no longer any concerns over cache misses.

http://www.tgdaily.com/content/view/38009/135/

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wutske

so, by integrating dram into a cpu you will not have any cache misses ??? That makes no sense ... unless you store everything on the cpu and don't use different levels of cache (few MB), primairy memory (few GB) and virtual memory (even more GB) ...

Kougar

A cache miss also has to do with the processor core operating faster than the L1/L2/L3 caches. The CPU wastes cycles while it waits for cache latency, and if you miss the access window you waste double the cycles to access the data before the CPU can start crunching that data.

Here it sounds like the cache would operate in sync with the rest of the CPU core... instant access to cache data at whim, almost.

wutske

ah, that sort of cache misses