Stefan Mileschin

JEDEC still has not published the DDR5 specification officially, yet it looks like DRAM makers and SoC designers are preparing for the DDR5 launch at full steam. Cadence, which was vocal about the new technology back in 2018, and has since released provisional DDR5 IP (the DDR5 controller and PHY) commercially, this week presented some additional information about the upcoming DDR5 market release as well as the technology's progress.
DDR5 Platforms Getting Ready

On the SoC side of matters, we already know that AMD’s EPYC ‘Genoa’ as well as Intel’s Xeon Scalable ‘Sapphire Rapids’ will support DDR5 DRAM when they launch in the 2021 ~ 2022 timeframe. What is noteworthy, is that Cadence’s provisional DDR5 IP has ‘over a dozen design-ins’, so there are over 12 SoCs supporting DDR5 in various stages of development right now. Some of these system-on-chips will come earlier and some will be available later, but it is evident that there is a serious interest towards the technology among developers of SoCs.

Cadence is confident that its DDR5 controller and PHY are compliant to the formal JEDEC specification, so SoCs that use its IP will be compatible with upcoming DDR5 memory modules.
https://www.anandtech.com/show/15671...in-development