Stefan Mileschin

CERN engineer Liviu Valsan, in a recent presentation on datacenter hardware trends, presented a curious looking slide that highlights some of the key features of AMD's upcoming "Zen" CPU architecture. We know from a recent story that the architecture is scalable up to 32 cores per socket, and that AMD is building these chips on the 14 nanometer FinFET process.

Among the other key features detailed on the slide are symmetric multi-threading (SMT). Implemented for over a decade by Intel as HyperThreading Technology, SMT exposes a physical core as two logical CPUs to the software, letting it make better use of the hardware resources. Another feature is talk of up to eight DDR4 memory channels. This could mean that AMD is readying a product to compete with the Xeon E7 series. Lastly, the slide mentions that "Zen" could bring about IPC improvements that are 40 percent higher than the current architecture.

http://www.techpowerup.com/219993/am...-channels.html