AMD has problems with power leakage on their 65nm CPUs

Sidney · 22nd July 2007, 07:03

Yesterday, we said we would talk about the prospects of AMD getting competitive K10 chips out.

We've suspected based on circumstantial evidence that AMD's core problem has been the 65nm SOI process.

Now someone has come up with some hard evidence that this in fact has been the case.

You really should look at the link; it's excellent detective work, but what the gentleman did was go to the AMD datasheets and compare the amperages used by various 65nm and 90nm AMD chips when in Halt/Stop Grant states (i.e., an idle state for CPUs).

http://overclockers.com/tips01182/

22nd July 2007, 10:49

That is rather interesting, I guess it's a pain in the *** if you produce 4 chip dies instead of 2 chip dies which would explain the yield problems with barcelona.

22nd July 2007, 21:13

Makes you wonder why they make the decision to not go with their new IBM/AMD developed high-K dielectrics and metal transistor process for the 65nm node in place of SOI. Instead they chose to use it for their 45nm parts next year, hopefully they will last that long while remaining in one piece.

22nd July 2007, 07:03	#1
Sidney Member Join Date: Mar 2004 Posts: 15,738	AMD has problems with power leakage on their 65nm CPUs Yesterday, we said we would talk about the prospects of AMD getting competitive K10 chips out. We've suspected based on circumstantial evidence that AMD's core problem has been the 65nm SOI process. Now someone has come up with some hard evidence that this in fact has been the case. You really should look at the link; it's excellent detective work, but what the gentleman did was go to the AMD datasheets and compare the amperages used by various 65nm and 90nm AMD chips when in Halt/Stop Grant states (i.e., an idle state for CPUs). http://overclockers.com/tips01182/ __________________ lazyman Opteron 165 (2) @2.85 1.42 vcore AMD Stock HSF + Chill Vent II

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22nd July 2007, 10:49	#2
Rutar Posts: n/a	That is rather interesting, I guess it's a pain in the *** if you produce 4 chip dies instead of 2 chip dies which would explain the yield problems with barcelona.

22nd July 2007, 21:13	#3
Kougar Posts: n/a	Makes you wonder why they make the decision to not go with their new IBM/AMD developed high-K dielectrics and metal transistor process for the 65nm node in place of SOI. Instead they chose to use it for their 45nm parts next year, hopefully they will last that long while remaining in one piece.