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AMD attacks DDR2 latency problems
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AMD attacks DDR2 latency problems
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24th March 2006, 11:16
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| Madshrimp  Join Date: May 2002 Location: 7090/Belgium
Posts: 79,022
 | AMD attacks DDR2 latency problems The answer is simple in theory. Add another level of cache, go for a big one and you’re home free. In fact, by creating a larger L3 cache, AMD will have the opportunity to reduce the size of L2 cache and save die space. 64+64 L1, 512KB or 1MB L2 and 2-4MB of L3 are the first things that comes to mind. The cache would of course, keep all two or four cores happy and keep the data flowing.
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