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Tabula Rasa Semantics, in Microprocessor Burn-in. Part-II
CPU by KeithSuppe @ 2003-07-01
Part II of Liquid3D's in-depth research into microprocessor technology, he takes it below zero and kicks it into overdrive!
Page 3
I believe we are at the most critical stages in semiconductor manufacture. With most IC makers either working in a "Fabless" environment, sourcing their wafers from SOI vendors, or researching and implementing their own version of SOI as Intel has, perhaps there will be more consistency among the next generations of die shrinks in that respect. Yet, CPU makers are in the midst of a most complex transition from DUV (Deep Ultraviolet Lithography) otherwise known as "soft" lithography (248nm) and the evolution towards EUVL (post 32nm, or .032 micron die). There's currently an integration of old and new technologies, and production cannot simply come to a standstill whilst designers occlude redundant technologies, incorporate and exclusively fine tune those technologies necessary. The following quote will exemplify many of the contentions made in this abstract:
The semiconductor industry's shift to 90-nanometer devices—with circuits 30% narrower than in the previous 130-nm (0.13-micron) generation—is turning out to be its toughest transition yet...Besides smaller circuit geometries, chip makers are struggling to deploy a host of new materials, process technologies and design tools while dealing with increasingly complex trade-offs between speed, power consumption and manufacturing yields. Complicating matters, many companies are also in the midst of expensive upgrades from 200-mm to 300-mm wafers, which lower per-chip costs but require expensive new manufacturing tools...It's becoming more costly and complex...That's part of the reason you're seeing this narrowing of the number of companies building their own chips these days...Still, the attractions of 90-nm technology—which allows chip makers to squeeze nearly twice as many transistors onto the same amount of silicon—are undeniable, and nearly every chip maker is working on the technology....the challenges are formidable. Besides tighter lithography for etching smaller circuits, chip designers must deal with numerous side effects. Reducing the amount of insulating silicon between circuit wires, for instance, increases both current leakage and signal interference unless designers take corrective steps....90-nm designs are expected to use low-k dielectrics, insulating materials that reduce interference. Several chip makers also plan to use silicon-on-insulator (SoI) technology in their 90-nm designs, a way of chemically treating silicon wafers to provide better insulation, which can boost performance and save power. Santa Clara, CA-based Intel Corp. is bypassing SoI for now but plans to use "strained" silicon, a way of stretching silicon atoms further apart than usual, to reduce electrical resistance and make its chips faster..
Intel has "bypassed" SOI, however this is not temporary, and they’ve taken the technology one logical step further. As I mentioned in my earlier discussion of CMOS technology, capacitance, and leakage, this is a critical area in microprocessor design. Still even SOI has its imperfections, however; Intel’s methodology seems to have integrated the best of both worlds. Intel has developed what is known as Strained Silicon on Insulator (SSOI). This process should have a significant affect on performance, and may be the ideal exponent for all future Fabrication process. It's actually a much simpler approach to a very complex problem, in that it steps back to the basics of silicon as a semiconductor, to leap forward in voltage, capacitance and speed in transistors. This is how it works:
Intel has integrated its own implementation of high-performance strained silicon...The benefits of strained silicon are that electron and hole mobility is increased in transistor channels, resulting in a 10-20% increase in transistor drive current...The process doesn't degrade transistor short-channel behavior or junction leakage, and adds only ;2% to total processing costs...Strained silicon technology takes advantage of the natural tendency for atoms inside compounds to align with one another. When silicon is deposited on top of a substrate with atoms spaced farther apart, the atoms in silicon stretch to line up with the atoms beneath, stretching — or "straining" — the silicon. In the strained silicon, electrons experience less resistance and flow faster...experts note that one challenge is maintaining the level of strain through the thermal processing cycles. A higher germanium content in the relaxed silicon germanium layer results in more strain in the active strained silicon layer. The strain stretches the silicon atoms slightly, allowing much faster transport of the electrons in NMOS, and to a lesser extent, the holes used as carriers in the PMOS devices...By combining the faster transport properties of the strained silicon channels with the lower leakage current of SOI, performance and power consumption can be improved sharply. But companies naturally worry about costs. Moving SSOI technology to volumes requires affordable SSOI substrates, and a design methodology that removes the complexity of dealing with the history effect of SOI.
The pictures below (from IBM) show the containment properties of SSOI. The minimal leakage not only conserves energy, speeds the circuit, it also reduces thermal effects.
Initially I found it somewhat difficult to discern any "dramatic" differences in the enlargement. Upon further scrutiny I realized the photo on the left almost looks "doctored" to accentuate the light, however; it is in fact the result of resistance and elevated temperature. In the photo (SSOI) on the right, current flows with greater efficiency, lower temperature, less capacitance and emits less "glare". On the left the "glare" is actual electro migration resulting from the violent bombardment of electrons in and upon each other, and of course the heat associated with this effect. If a picture's worth a thousand words, we may be entering a new era, in overclocking prowess. The SSOI substrate not only seems to run much cooler, but with less resistance, and reduced capacitance speeds should be greatly increased.
The transition to .09 micron, albeit fraught with complexities, has also motivated manufacturers to research, and implement numerous changes.
SSOI (in Intel's case) and Low-k dielectrics should yield some amazing results. It's my opinion the 90-nm node (.09 micron) will take us into 5.+GHz, and perhaps 6.+GHz in extreme overclocking scenarios. Although lithographic techniques have by no means made a complete departure from DUV, however; it's exciting to know we will see at least 10GHz by 2007.
In my last paper I imprudently predicted 30GHz by 2007, and while is certainly feasible, microchip makers will not eschew well over 54 chipset models to do so. And that's certainly underestimating the figures. It's quite frustrating knowing the technology exists, yet being staggered. On the other hand it takes a significant profit margin to drive such costly research, and manufacturing industry rivaling Space exploration in its manufacturing costs. As CPU's become faster, and their architecture more diverse, their computational power exponentially increases with every die-shrink, unfortunately with every die-shrink esoteric complications increase as well. I'm confident SOI/SSOI has already had a major impact upon thermal effects. And with companies such as Chip-Con committed to ameliorating those effects (albeit ad hoc) it's exciting to see where the two will merge.
In the last part of this 3 part Article I will go into the Burn-In process:
Hold on tight for this last part!
Comments, questions and suggestions can be placed in this thread @ our forums (no registration)
The semiconductor industry's shift to 90-nanometer devices—with circuits 30% narrower than in the previous 130-nm (0.13-micron) generation—is turning out to be its toughest transition yet...Besides smaller circuit geometries, chip makers are struggling to deploy a host of new materials, process technologies and design tools while dealing with increasingly complex trade-offs between speed, power consumption and manufacturing yields. Complicating matters, many companies are also in the midst of expensive upgrades from 200-mm to 300-mm wafers, which lower per-chip costs but require expensive new manufacturing tools...It's becoming more costly and complex...That's part of the reason you're seeing this narrowing of the number of companies building their own chips these days...Still, the attractions of 90-nm technology—which allows chip makers to squeeze nearly twice as many transistors onto the same amount of silicon—are undeniable, and nearly every chip maker is working on the technology....the challenges are formidable. Besides tighter lithography for etching smaller circuits, chip designers must deal with numerous side effects. Reducing the amount of insulating silicon between circuit wires, for instance, increases both current leakage and signal interference unless designers take corrective steps....90-nm designs are expected to use low-k dielectrics, insulating materials that reduce interference. Several chip makers also plan to use silicon-on-insulator (SoI) technology in their 90-nm designs, a way of chemically treating silicon wafers to provide better insulation, which can boost performance and save power. Santa Clara, CA-based Intel Corp. is bypassing SoI for now but plans to use "strained" silicon, a way of stretching silicon atoms further apart than usual, to reduce electrical resistance and make its chips faster..
Intel has "bypassed" SOI, however this is not temporary, and they’ve taken the technology one logical step further. As I mentioned in my earlier discussion of CMOS technology, capacitance, and leakage, this is a critical area in microprocessor design. Still even SOI has its imperfections, however; Intel’s methodology seems to have integrated the best of both worlds. Intel has developed what is known as Strained Silicon on Insulator (SSOI). This process should have a significant affect on performance, and may be the ideal exponent for all future Fabrication process. It's actually a much simpler approach to a very complex problem, in that it steps back to the basics of silicon as a semiconductor, to leap forward in voltage, capacitance and speed in transistors. This is how it works:
Intel has integrated its own implementation of high-performance strained silicon...The benefits of strained silicon are that electron and hole mobility is increased in transistor channels, resulting in a 10-20% increase in transistor drive current...The process doesn't degrade transistor short-channel behavior or junction leakage, and adds only ;2% to total processing costs...Strained silicon technology takes advantage of the natural tendency for atoms inside compounds to align with one another. When silicon is deposited on top of a substrate with atoms spaced farther apart, the atoms in silicon stretch to line up with the atoms beneath, stretching — or "straining" — the silicon. In the strained silicon, electrons experience less resistance and flow faster...experts note that one challenge is maintaining the level of strain through the thermal processing cycles. A higher germanium content in the relaxed silicon germanium layer results in more strain in the active strained silicon layer. The strain stretches the silicon atoms slightly, allowing much faster transport of the electrons in NMOS, and to a lesser extent, the holes used as carriers in the PMOS devices...By combining the faster transport properties of the strained silicon channels with the lower leakage current of SOI, performance and power consumption can be improved sharply. But companies naturally worry about costs. Moving SSOI technology to volumes requires affordable SSOI substrates, and a design methodology that removes the complexity of dealing with the history effect of SOI.
The pictures below (from IBM) show the containment properties of SSOI. The minimal leakage not only conserves energy, speeds the circuit, it also reduces thermal effects.
Initially I found it somewhat difficult to discern any "dramatic" differences in the enlargement. Upon further scrutiny I realized the photo on the left almost looks "doctored" to accentuate the light, however; it is in fact the result of resistance and elevated temperature. In the photo (SSOI) on the right, current flows with greater efficiency, lower temperature, less capacitance and emits less "glare". On the left the "glare" is actual electro migration resulting from the violent bombardment of electrons in and upon each other, and of course the heat associated with this effect. If a picture's worth a thousand words, we may be entering a new era, in overclocking prowess. The SSOI substrate not only seems to run much cooler, but with less resistance, and reduced capacitance speeds should be greatly increased.
The transition to .09 micron, albeit fraught with complexities, has also motivated manufacturers to research, and implement numerous changes.
The 90 nm generation is all about control: controlling CDs, overlay, defect levels on reticles and wafers, film thickness, dopant levels, dishing and erosion, stress between films, etc. All yield issues intensify with each technology generation. But the need to separate yield-killing defects from nuisance defects becomes especially important as you approach 90 nm.
SSOI (in Intel's case) and Low-k dielectrics should yield some amazing results. It's my opinion the 90-nm node (.09 micron) will take us into 5.+GHz, and perhaps 6.+GHz in extreme overclocking scenarios. Although lithographic techniques have by no means made a complete departure from DUV, however; it's exciting to know we will see at least 10GHz by 2007.
In my last paper I imprudently predicted 30GHz by 2007, and while is certainly feasible, microchip makers will not eschew well over 54 chipset models to do so. And that's certainly underestimating the figures. It's quite frustrating knowing the technology exists, yet being staggered. On the other hand it takes a significant profit margin to drive such costly research, and manufacturing industry rivaling Space exploration in its manufacturing costs. As CPU's become faster, and their architecture more diverse, their computational power exponentially increases with every die-shrink, unfortunately with every die-shrink esoteric complications increase as well. I'm confident SOI/SSOI has already had a major impact upon thermal effects. And with companies such as Chip-Con committed to ameliorating those effects (albeit ad hoc) it's exciting to see where the two will merge.
In the last part of this 3 part Article I will go into the Burn-In process:
There are a great many overclockers who swear by the benefits of Burn-in, even from a prima facie perspective it "seems" logical. Yet, truth of the matter is, the moment current begins to pass through an electronic device, its finite existence is predestined.
Hold on tight for this last part!
Comments, questions and suggestions can be placed in this thread @ our forums (no registration)
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