Kingston is one of the largest memory manufacturers on the market today. Their products can be found in just about every type of computer, including Workstations, Server's, Desktop-PC's and High End Gaming rigs. When Kingston released their Hyper-X line it was an immediate success, among the discriminating PC-Enthusiast and Overclocker genre, which is undoubtedly a difficult crowd to please.

Several months ago Kingston introduced their Hyper-X line for DDR2 and if it performs on the same level of original Hyper-X we should have another winner on our hands. Today we'll be taking a closer look at Hyper-X KHX5400D2/512 Gigabit Kit and put it through its paces on the venerable Abit AA8 motherboard. Based on the Intel i925X chipset, this board features all the “BIOS tweaks” and accoutrement's any dedicated Overclocker might desire.

Kingston has made some of the most reliable memory, always priced competitively, and often possessing the innate ability to perform beyond its specifications. Today we'll discover just what the innate capabilities are in Kingston's KHX5400 as we have a highly overclockable P4 530 (also known as a 3Ghz Prescott) to test it with. Looking back at an article I wrote about DDR2 some time ago, I must correct some errors. I incorrectly claimed DDR2 “....ran quite hot..” my error was common among those who didn't first hand knowledge into the standard, and how it might work. At that time there were more then a few articles such as this from CPU-Planet, which claimed early DDR2 ran hot. With all due respect to the aforementioned author, any theories formulated about DDR2 at that stage were based on the only working examples of the memory, which happened to be on graphics cards.

The fact is, today's DDR2 memory uses FBGA (Fine Ball Grid Array) packaging which runs at lower voltage (1.80V) and theoretically produces less heat. In an upcoming article I'll be measuring the differences in heat output between DDR and DDR2. For complete DDR2 specifications, JEDEC (Joint Electron Device Engineering Council) has released a white paper JESD79-2A detailing the standard, which currently includes four speed grades:
- DDR2 400
- DDR2 533
- DDR2 667
- DDR2 SS800

Te latter may not be far off. From the following news at OCZ Technology it seems they are close to releasing DDR2 SS800. Although DDR2 was first discussed as a standard back in 1998, it is developing rapidly. Of course given the fact there's no discernible speed advantage from DDR1 400 to DDR2 400, and there's already DDR2 533, it seems logical to me DDR2 667 should be on the market.

To explain DDR2 as simply as possible, the graphs below borrowed from Digit-Life, are by far the clearest I've found. First let's look at how DDR1 works:





With DDR the following occurs:

- The CPU requests data from a specific memory address.
- That request is then passed to the MCH (Memory Controller Hub) which then instructs the DRAM to open a specific bank where the data resides.
- That request is made, the data is retrieved and deposited onto the DRAM's output pins.
- Data buffers on the DRAM module are used to buffer data prior to being deposited on the module's out-put pins. It's the manner in which these buffers function compared to DDR2 I/O buffers which differentiate the two standards, at least functionally.

With DDR the data buffers and memory core operate at the same frequency. Two bits of data are retrieved, and deposited back to the module's output pins. That data will then be output on the rising and falling edge of the clock cycle, hence the term Double Data Rate. By JEDEC standards DDR2 400 will pick up where DDR1 400 leaves off, and the graph above exemplifies the core frequency for DDR1 400. While there are obviously faster DDR speeds, for our purposes it's clearer to use models based on the current JEDEC standards. Now let's take a look at how DDR2 works:





- With DDR2 the CPU makes a data request which is passed to the MCH (most likely using a divider).
- The request passed to the MCH, which instructs the DRAM to open a specific bank.
- With DDR2 the data buffers operate at twice the speed of the core frequency, and are fetching four data bits. This is then doubled on the output frequency, on the falling and rising edge of the clock cycle (Double Data Rate).

The primary complaint about DDR2 is the higher latencies, and it's precisely the amount of bank activity which contributes to these higher latencies. It simply takes more time to retrieve four bits of data, therefore commands such as tRAS are higher, because the address (or bank) must remain open longer while the data is queued. There are, however; several attributes innate to DDR2 which outweigh its chief complaint.

First, the core frequency operates at just half that of DDR1 at lowering voltage requirements while concurrently running at higher frequencies. This coincides with microprocessor scaling, as the memory core resides on a smaller die. As DDR2 speeds increase, so too will bandwidth, until a balance is ascertained once again. Latencies may tighten somewhat as manufacturers become more familiar with the .09-micron die, and the standard's characteristics.

Onto our practical tests ->